Advanced Packaging Conference (APC)

    Material and Process Challenges in the Era of Digital Transformation

    Advanced packaging of electronics is an integrated part of the system solutions required to enable digital transformation in applications such as Autonomous Driving, Automotive Wireless Communication (combined with 5G), AI (Artificial Intelligence), AR/VR (Augmented Reality/ Virtual Reality), Medical Devices, Industrial Manufacturing, Data Processing and Storage, Cloud Computing, IoT (Internet of Things), Intelligent Sensors and other key trends. Artificial Intelligence will move towards quantum applications e.g. computing, sensing and communications, photonic-electronic advancements, low temperature operation in computing and sensing.

    The Digital Transformation of Electronics Packaging, particularly of ICs (Integrated Circuits), Sensors and MEMS (Micro-Electro-Mechanical Systems), MOEMS (Micro-Optoelectronic Mechanical Systems) and Photonics dies is gaining more and more relevance in today’s industry applications. Especially for AI, AR/VR and IoT the performance, formfactor and cost are significant indicators. Miniaturization and an increasing level of integration at packaging level targets more functionality on less space, which is promising higher system performance, smaller system size and lower system cost. This requires a system-level approach with Chip-Package-Board co-design and co-development with a close cooperation along the complete semiconductor supply chain.

    New advanced packaging solutions can’t be developed in isolation. They require manufacturing equipment with advanced capabilities, processing new functional materials, with manufacturing process IP developed in-house or provided by third parties. EDA (Electronic Design Automation) and Simulation tools and methods need to be enhanced for SiP, and Chip-Package-Board co-design. ADK (Assembly Design Kits) need to be developed and linked to PDK (Process Design Kits) of chip design and wafer manufacturing technologies. Design for reliability and design for test is required. To shorten development time and reduce cost significantly, there is a greater need for electro-magnetic performance, thermal and thermo-mechanical simulation at the package level, or ideally a complete virtual prototyping environment. A collaborative approach with new ideas, close co-operations, alliances, partnerships and new business models along the semiconductor supply chain is required.

    If your company is part of the semiconductor supply chain, and you are contributing with innovations, new developments, concepts, partnership, business models or roadmaps in regard to Material and Process Challenges in the Era of Digital Transformation, you are invited to submit an abstract.

    Submitted papers should cover Packaging/Assembly and Wafer/Package Test innovation and new developments in Design, EDA, ADK, Simulation, Manufacturing Equipment, Material and Process IP enabling Heterogeneous Integration in Package for new Applications We encourage participation from companies and individuals that can demonstrate advancements in the following areas:


    • Advanced packaging and interconnect technologies
    • Artificial Intelligence; quality improvement and control of package production; reliability, low temperature operation on computing and sensing
    • SiP; MEMS and Sensor integration for IoT
    • Optoelectronics, Photonics; optical communication
    • UV-LED for virus disinfection, miniLED and microLED assembly and repair
    • Packaging and integration in SiP
    • High Voltage and Power Packaging
    • Chip embedding Packaging Technologies
    • Wafer-Level Packaging (Fan-In and Fan-Out)
    • Automotive; Packaging for Lidar and ADAS
    • Wafer to wafer bonding; package and design requirements
    • Chip-Package-Interaction (CPI) and Reliability
    • Modeling, Simulation, Virtual Prototyping; New functional packaging materials for higher reliability and yield
    • Thin wafer/panel handling
    • Quality and reliability assurance
    • Metrology and inspection methods
    • Failure modes and analysis
    • Cost reduction of advanced packaging
    • Green Packaging; sustainability targets
    • Markets and Applications

    Wafer/Package Test:

    • SiP test concepts (partially and fully assembled)
    • BIST (built-in self-test), redundancy and repair
    • Test of high frequency applications e.g. 5G
    • Wafer-Level Package handling and test
    • Probing and alignment for small contact pitches
    • Overcoming packaging limits to enable test at high parallelism
    • Packaging and test: strategies for high-energy alpha wave sensitive materials
    • Validation of interconnects at multiple temperatures (room, hot and cold)
    • Validation of interconnects at high power (high voltage and/or current)
    • Validation of interconnects at microwave frequencies
    • Test strategies for multi-chip packages
    • Testing packages with integrated sensors
    • Testing packages with integrated antennas
    • Fine-pitch testing; effectivity
    • Contactless testing
    • Using simulation to optimize test interconnect solutions

    General guidelines

    • Please submit your abstract, biography and a photo through our link by 28th June 2021.
    • Abstracts submitted via other methods will generally not be accepted.
    • The conference language is English.
    • The abstract should have between 250 and 500 words (Starting with descriptive paragraph identifying issue addressed and solution). Please focus on the news instead of describing state-of-the-art.
    • Abstract modifications, changes and corrections will be accepted until 5th July 2021.
    • Selected presenters will be notified in July 2021.

    Your presentation may not be included in the review process unless the information is complete. Evaluation criteria include significance, usefulness for the manufacturing world and clarity and accuracy as a paper. Abstracts will be peer-reviewed and selected relative to the points above. We encourage application related presentations, i.e. on joint projects between users and suppliers. Papers are to be non-commercial and focus on the technical/economical merits of a process rather than the individual company’s product benefits.



    SEMI Europe Advanced Packaging Conference (APC) Committee:

    • Steffen Kroehnert, ESPAT-Consulting (Chair)
    • Peter Cockburn, Cohu (Co-Chair)
    • Jonathan Abdilla, Besi
    • Rolf Aschenbrenner, Fraunhofer IZM
    • Mark Azzopardi, CMT Semiconductor
    • Ruud De Wit, Henkel
    • Ivan Galesic, OSRAM
    • Michel Garnier, STMicroelectronic
    • Matthias Grossmann, Momentive
    • Ingo Henkel, Bosch
    • Cassandra Koenig, Advantest
    • Frank Kuechenmeister, GLOBALFOUNDRIES
    • Andy Longford, PandA Europe
    • Andy Miller, IMEC
    • Jens Mueller, IMAPS Europe Chapter
    • Pascal Oberndorff, NXP
    • Thomas Oppert, PacTech
    • Gabriel Pares, CEA-LETI
    • Klaus Pressel, Infineon
    • Roland Rettenmeier, Evatec
    • Ralf Schmidt, Atotech


    See information in PDF here.
    Official website

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